Advanced packaging is a set of techniques used in the semiconductor industry to combine multiple chips or components into a single package. It goes beyond traditional chip packaging by allowing for the integration of different types of devices, such as memory, processors, and sensors, into a single unit. This approach offers several benefits, including increased performance, reduced power consumption, and smaller form factors.  

In this complex three dimensional world, architectural exploration and connectivity management play crucial roles in achieving optimal performance, power efficiency, and cost-effectiveness.

Architectural exploration (partitioning, placement, technology selection, etc.) is the key factor for the system definition since this involves determining the optimal organization of different dies (chiplets) in the 3D stack.

Connectivity Management focuses on designing the intricate network of interconnects that link the chiplets together, leading to faster signal speeds, lower latency, reduced overall size and weight of electronic devices.

This video will highlight the key role GENIOEVO is playing in Advanced Packaging Architectural Exploration and Connectivity Management.

3D heterogeneous integration is a promising technology that can improve the performance and power efficiency of microelectronic devices. However, there are several technical challenges created by the combined effects of several different physical factors (electrical, thermal, mechanical) that need to be solved all together to make it a successful design approach.

A Multi-physics design cockpit, a specialized software environment that enables engineers to design and analyze complex 3D integrated circuits (ICs) while considering the interplay of various physical phenomena, is a crucial tool for enabling the successful development of advanced 3D heterogeneous systems in microelectronics.

This video will highlight the key role GENIOEVO is playing as a Multi-physics cockpit for 3D heterogeneous integration.

MZ Technologies, a leading supplier of innovative solutions and methodologies for 2.5 and 3D design, will be exhibiting at Chiplet Summit, January 21-23, at the Santa Clara (CA) Convention Center.

MZ Technologies envisions, develops and delivers software automated solutions that facilitate the design and optimize connections in complex, heterogeneous IC systems. Highlighting the company’s presence will be the unveiling of GENIO EVO, the first integrated chiplet/package EDA tool to address in pre-layout stage the two major issues of 3D-IC design, thermal and mechanical stress.

GENIO EVO is the second generation of GENIO™, which was the EDA’s first successful integrated chiplet/package co-design tool. GENIO, MZ’s flagship product, is a cross-fabric platform for system design providing chiplet/die, silicon interposer, package, and surrounding PCB co-design features that achieve area, power, and performance targets. The tool is technology agnostic and seamlessly integrates through standard formats with all the existing commercial implementation platforms or to custom EDA flows through dedicated plug-ins.

Like the original, GENIO EVO fits into any existing design flow and operates at the architecture level, pathfinding the optimal system choices to implement a 2.5D or 3D multi-die design.

A new user interface fronts a cross-hierarchical, 3D-aware design methodology that streamlines the entire system design process. IC and advanced packaging design are integrated to ensure full system level optimization, with a shorter design cycle, faster time-to-manufacturing, and improved yields.

GENIO EVO provides additional identification and analysis of thermal and mechanical failures. It promotes architectural exploration and what-if analysis during early stages of design to improve predictability during implementation. It anticipates and avoid downstream thermal and mechanical issues by planning & managing high pin count interconnect in complex multi-fabric system design.

“Chiplet Summit is the perfect place to introduce GENIO EVO to the EDA world because it truly is the first “ground-up” design tool to tackle the complexity of chiplet/package co-design. What’s more, it’s available today for immediate licensing,” said Anna Fontanelli, founder and CEO of MZ Technologies.

MZ Technologies has unveiled an updated technology roadmap for its GENIO™branded integrated chiplet/packaging Co-Design EDA tool.

The roadmap calls for major improvements throughout 2025, starting with four major additions to a new GENIO’s product that will be unveiled in the mid-January timeframe.  Other new features will be added around mid-year and at year’s end.

The new features to be announced at the first of the year address some of most vexing advanced systems challenges. The latest vision calls for tackling thermal and mechanical issues. and will be accompanied by an improved and modernized user interface.  Mid-year, MZ is expected to add additional thermal and interconnect features

Thermal and Mechanical Stress Barriers

The new thermal and mechanical features respond to thorny considerations in next-generation 3D-ICs.  In 3D-packed heterogeneous semiconductor devices, thermal stress arises from uneven heat distribution during operation, potentially leading to warping and reliability failures. Effective thermal management strategies are essential to minimize temperature differentials, ensuring optimal performance and longevity of the integrated chiplets within the package.

Mechanical stress in 3D-packed designs can result from factors such as thermal expansion mismatch and substrate flexing. These stresses can cause interconnect failures or delamination. A robust design framework must address these challenges to maintain structural integrity and performance across varying operational conditions and material interfaces.

First Available Integrated Co-Design Tool

GENIO’s proprietary, fully integrated EDA co-design tool features an end-to-end IC and packaging platform for 2D/2.5D/3D system design.  It integrates existing silicon and package EDA flows to create full co-design and optimization of complex multi-chip designs that comprise advanced heterogeneous microelectronic systems.  

““”MZ Technologies rolled out the first commercially available co-design tool three years ago and we feel an obligation to the EDA community to continue to innovate.” said Anna Fontanelli, Founder and CEO of MZ Technologies.  

GENIO’s cross-hierarchical, 3D-aware, design methodologies streamline the entire IC eco-system.  It integrates IC and advanced packaging design to ensure full system level optimization, shorten the design cycle, drive faster time-to-manufacturing and improve yields.

MZ Technologies is a unique company that enables multi-die design by providing critical planning and analysis tools that sit above the traditional EDA design flow. Chip and package design tools are good at what they do. Given a set of constraints, they will deliver a good result. The question is, what is the right set of constraints?  What type of stack (for 3D), what type of interposer (for 2.5D) and what type of placement of blocks and pins will deliver the best result?  These are just some of the questions MZ Technologies addresses. The company’s design tool is called GENIO™. I got an opportunity to see a live demonstration of the tool recently. That illuminated a lot about its impact. Read on to see how MZ Technologies enables multi-die design with GENIO.

If you want some background on MZ Technologies and how its products fit in the design flow, you can get that here. As they say, a picture is worth 1,000 words. A live demo has similar power to illuminate concepts. Let’s dig in…

GENIO for 2.5D

Francesco Rossi, engineering manager at MZ Technologies began the demo by developing a 2.5D design consisting of an XPU and four HBM memory stacks. Using simple and intuitive “drag and drop” capabilities and library managers, he configured items such as the four HBM stacks, the XPU, the PHYs for each HBM and a silicon interposer.  Bump locations were also defined for the interposer to handle connectivity between components and through the silicon interposer to the package substrate. Connection points on the package were also defined with GENIO in a straight-forward manner.

Below is a screen shot of the graphical representation of the completed stack.

Once the complete stack was defined (package, interposer, devices), connectivity was introduced and optimized. The optimization process examined the fly lines implied by the connectivity to minimize overall fly line length. This will deliver a more optimal starting point for the downstream implementation flow. Consideration was also given to ensure there were no crossovers in the fly lines. The figure below shows the results of this work. All fly lines are displayed. The red items are through-silicon vias (TSVs). These have been either automatically placed or guided by the designer for critical areas.

Anna Fontanelli, founder and CEO at MZ Technologies also joined the demo. She explained that this demo was developed in conjunction with Synopsys to ensure a good fit between GENIO and the implementation tools and IP that it works with. She said that Synopsys DesignWare IP was used for the demo, which interfaced with Synopsys IC Compiler and Custom Compiler. The key point was a good flow between the high-level planning offered by GENIO and the tools and IP that would ultimately implement the final system.

She went on to explain that this design had over 200,000 nets. The interconnect cockpit provided by GENIO delivers substantial new capabilities to manage and optimize a problem of this size. For example, pin groupings can be defined that cross the entire design hierarchy. Fly lines and group of fly lines can be analyzed for average, min and max length. She pointed out that analyzing the design across the full hierarchy, from silicon all the way to the package provides a unique perspective on system performance that is difficult to achieve with conventional approaches.

Using these, and many other capabilities the aspect ratio of the initial design can be examined to ensure an optimal result. Slight changes in aspect ratio and placement can be quickly assessed to find the best result. Anna also explained that estimated resistances can be extracted from the interconnect to drive early static timing analysis.

GENIO for 3D

Marco Cignarella, senior software engineer at MZ Technologies showed how GENIO can be used to define and optimize 3D stacks. A design consisting of multiple chips and memories was used. By changing the stack configuration, the overall interconnect length and number of TSVs can be quickly assessed. Key relationships about the relative placement of components in the 3D stack can be easily specified before optimization begins. This allows global designer perspective to be considered with minimal intervention.

Using these capabilities, the top two or three stack configurations can be quickly identified for further analysis. Below are screen shots of one candidate 3D stack configuration and the associated fly line routing view. A lot of global perspective can be achieved in a short period of time.

To Learn More

This demo session provided an incredible amount of design perspective and analysis in a short period of time. I am sure many design teams work to develop the optimal configuration for a 2.5D or 3D design using Microsoft Excel and PowerPoint. The data that drives these analyses is often scattered across multiple directories.

The ability to do this work in one “cockpit” with one, verified data source and automated analytics and visualization tools can take a multi-week project down to a day or so, with far better results. If you are considering multi-die design, you need a tool like GENIO. The ways to contact MZ Technologies can be found here. And that’s how MZ Technologies enables multi-die design with GENIO.

About MZ Technologies

I mentioned pathfinding. In the context here, the term refers to identifying the optimal technology choices to implement a 2.5D or 3D multi-die design. The problem has been around for quite a while. Here is a discussion of it from the 2009 IEEE International Symposium on System-on-Chip. I have some experience with these problems as well. Around this same time frame while I was at Atrenta, we developed an early tool to address the pathfinding problem. And later, while at eSilicon, I got an up-close look at how challenging 2.5D design can be.

MZ Technologies was founded in 2014 by a team of leading EDA, IC, and package co-design experts. The goal was to build new technology from scratch to deal with the I/O planning and optimization phase of the physical implementation of complex 2.5D and 3D integrated circuits. That is, solve the pathfinding problem. A bit about the name of the company, which is shorthand for monozukuri. In Japanese, “monozukuri” is a compound word comprising “mono”, which literally means “things” (“products”), and “zukuri”, which means “process of making” or “creation”.

The company is a European EDA provider delivering GENIO™ a unified cockpit for 2.5D & 3D chiplet-based system design. GENIO is a tool that fills the pathfinding gap for multi-die design. It doesn’t compete with existing technologies, but rather interfaces with them to create a broader, more holistic capability. The tool has been around through several releases and has seen application across a wide range of multi-die designs. More on that in a bit.

What MZ Technologies Does

GENIO addresses the system architecture and IC/package co-development flow. This is the part of the design process that typically sits above existing tools and IP. It answers critical questions about the best implementation approach from a form factor, energy, performance, and cost point of view. Getting these things right early in the process can be the margin of victory for a complex design. Starting with a sub-optimal approach will create re-work, overruns, and a good chance the project will fail.

The figure below shows how GENIO fits into the overall design flow with existing tools.

The tool fits in the flow from concept to design to deliver a first time right optimal result. The goal is to create better manufacturability with optimal resources usage and better yield. GENIO works across the complete design ecosystem from silicon to package to PCB, with integrated design flows.

Digging a bit deeper, system architecture exploration is supported for planning, implementation, and analysis across different engineering domains. What-if analysis is provided for 2D, 2.5D and 3D interconnect management, I/O planning, and optimization. For example, planar vs. SI-based vs. 3D-stack. The optimization algorithms tame multi-die design computational complexity. Early estimations of electrical, mechanical, and thermal behavior are also provided.

With GENIO, it is possible to optimize in one shot through the full system hierarchy, from the top level to subsystems and components. A sophisticated GUI allows cross-highlight and scripting, among other functions, with the ability to go back in the design history to tag the most promising configurations.  The figure below shows an example of the GUI.

GENIO has delivered a remarkable 60x reduction of architectural design time. The table below illustrates the types of designs GENIO has been applied to.

Here is a summary of the current version and next generation of the tool:

GENIO V1.x (commercially available today with a back-end orientation)

• Comprehensive system view spans the entire design ecosystem
  • Cross-fabric platform, integrated with traditional IC, package & PCB design tools
• System-level architecture exploration
  • Identifies the more efficient and cost-effective option into 3D system offering
• Single, consistent Interconnect Manager
  • Represent and maintain the 3D model of the entire system
• Cross-hierarchical 3D-aware pathfinding
  • Constraint-driven, proprietary optimization algorithms
• 3D chiplet-based design flow with multiple IP libraries
  • Die stacking and silicon-to-silicon vertical communications – mix-and-match “LEGO-like” assembly 

GENIO EVO (Next Evolution release; introduces simulation-aware optimization)

• Complete 3D system view across physical implementation and analysis
• Super-fast parasitic estimation for early analysis
  • What-if analysis before physical implementation starts
• State-of-the-art TSV modeling
  • Including electrical performance (R/C) and mechanical/thermal behavior
• Thermal modeling
  • Based on power dissipation map and TSVs contribution
• Mechanical stress
• Voltage and temperature monitor placement according to identified thermal hotspots
  • Critical net group spotting and prioritization

• 3DBlox language support
• 3D-system partitioning flow
  • Support to system partitioning in the early stages of RTL & synthesis
• 3D-stack floor planning
  • Best positioning of system components/chiplets across the stack planes

To Learn More

MZ Technologies licenses its software with a time-based model. Additional services for custom integration, custom module development, and customer training are also available. If you are planning to tackle a multi-die design, you should contact them. I can tell you from first-hand experience the problem MZ solves is very real and can become a fatal flaw if not addressed early. You can reach out at info@monozukuri.eu. And that’s how MZ Technologies is making multi-die design a reality.

Gordon Moore predicted the demise of Moore’s law and envisioned in its place larger systems built from smaller, separately packaged, interconnected systems, according to Anna Fontanelli, Monozukuri S.p.A. CEO and Founder.Opening her presentation yesterday on innovative advanced packaging approaches during the IEEE EDAPS 2023 Hybrid Conference, at the Sugar Beach Resort, Wolmar, Flic-en-Flac, Republic of Mauritius, Ms. Fontanelli said that the semiconductor visionary accurately predicted stacked-die advanced packaging technology as the innovation successor to his own Moore’s law. She used Moore’s long-range vision to define the Advanced Packaging landscape and outlined chiplet and package co-design challenges.

Ms. Fontanelli summarized Advanced Packaging as combining different heterogeneous integration techniques, including multi-chip modules, through silicon via 2.5 and 3D integration, fan-out wafer-level packaging, system-in-package, chiplet-based integration, and/or, system dis-aggregation and re-aggregation.  In other words, “everything but the chips,” she said. 

“The most demanding IC systems today combine multiple components such as chiplets, memory and ASICs.  The package poses the challenge of handling, updating & optimizing complex interconnects in a 3D space,” Ms. Fontanelli explained.

Present-day 3D chiplet architecture demands die stacking and silicon-to-silicon vertical communications capabilities using a mix-and-match “LEGO-like” assembly.  This new chiplet packaging requires new tools, new methodologies, and new flows, she explained. 

One newly available choice is MZ Technologies’ GENIO^TM, the first integrated IC/Packaging EDA tool.  GENIO^TM is an advanced design environment integrating traditional silicon, package, and PCB design flows in one single flow. It provides capabilities for system architecture exploration, what if analysis, and I/O planning & optimization, using proprietary algorithms that efficiently map 3D interconnects.

GENIO^TM doesn’t overlap with existing technologies, rather it fills the gaps left open by of the major EDA tools.  To that end, new functionalities are related to timing/power/thermal analysis and physical manufacturability.

Ms. Fontanelli explained how the GENIO^TM holistic design environment spans the complete 3D design ecosystem.  Its co-design platform enables a revolutionary approach to integrating with physical implementation tools in both IC and package design spaces, as well as performing signal, power integrity, and pre-layout thermal estimation for physical-aware and simulation-aware system interconnect optimization.

She also revealed that on a real-design test case, GENIO^TM reduced architectural design time by 60X, cutting the process from three man-months to one-man day.

Read the entire interview here:

https://semiwiki.com/eda/mz-technologies/333571-ceo-interview-anna-fontanelli-of-mz-technologies/

Here’s some interview highlights:

• “We’re making good progress toward achieving the objective we set eight years ago … we’ve our technology and generated revenue across Asia and Europe, so now it makes sense for us to bring our expertise to North America.”
• “We’re taking on one of the industry’s thorniest problems: Creating the technology design nexus that transforms visions of the future into tomorrow’s innovative IC reality.”
• “GENIO™ redefines the co-design of next generation heterogeneous microelectronic systems by dramatically improving the automation of integrated silicon and package EDA flows through three-dimensional interconnect optimization.” 
• “There’s nothing like GENIO today, because it was built from the ground-up.  Most of the tools that attempt to do what GENIO does are what we refer to as “bolt-ons” … capabilities are literally mashed on to another in hopes of overcoming a new set of design challenges.”
• GENIO, is built from the ground-up.  Its system optimization from a unique dedicate cockpit that supports a 3D-aware cross-hierarchical pathfinding algorithm and a rule-based methodology that delivers single-step interconnect optimization throughout the entire 3D system hierarchy.”
• “The next generation of GENIO will extend the tool’s front-end capabilities for simulation-aware system interconnect optimization and early-on system analysis.  The early-on system analysis capability will be very robust.  It will include state-of-the-art TSV models with R/C electrical performance and mechanical/thermal behavior.  It will also provide thermal modeling based on power dissipation map and TSVs contribution.”

An internationally respected System/ASIC company is adopting MZ Technologies’ GENIO™ 1.7 fully-integrated EDA co-design tool.    

The company adopted a full-suite license and has targeted a next generation global semiconductor product family based on heterogeneous advanced technology system-in-package (SIP.)  Details of the design remain scant due to the propriety nature of the underlying technology.

The licensing agreement marks a major milestone for MZ Technologies, representing its initial entry into the broad Asian market.  

“To be the co-design tool of choice in the international marketplace is a huge step forward,” said Anna Fontanelli, Founder and CEO of MZ Technologies.  “It is global confirmation of the tool’s contribution to the future of chiplet-based and advanced hybrid package design.  

GENIO™ 1.7 is the first commercial integrated silicon/packaging co-design tool, available to IC and IC Package design leading companies.  Its cross-hierarchical, 3D-aware, design methodologies streamline the entire IC eco-system.  It integrates IC and advanced packaging design to ensure full system level optimization, shorten the design cycle, drive faster time-to-manufacturing and improve yields.

GENIO™ 1.7 co-plans the final packaged device and integrated electronic circuits (ICs) in complex 2.5-3D chiplet-based hybrid configurations and was recognized by an international jury of industry experts as a revolutionary EDA co-design tool. 

The GENIO^TM tool also easily integrates existing silicon and package EDA flows to create full co-design and optimization of complex multi-chip designs that comprise advanced heterogeneous microelectronic systems. 

GENIO^TM 1.7 licensed under this agreement features Parasitic Estimation and Stack Planning functionality that slash total design time and reduces overall design complexity.  
Parasitic Estimation enables early-on system analysis, based on virtual routes, prior to physical implementation.  Stack Planning Support automatically identifies the best 3D stack configuration, given physical and electrical constraints. It provides a more efficient chiplet-based 3D-IC system organization and electrical performance, while reducing the physical resources (TSVs) required for vertical interconnect.

Anna Fontanelli, Monozukuri S.p.A. CEO and Founder, demonstrated MZ-GENIO™, the first integrated IC/Packaging EDA tool, during the “Advanced 3D architecture and design methodology” session at DATE on Wednesday in Antwerp Belgium.   

During her session, Ms. Fontanelli showed how the MZ- GENIO™ holistic design environment spans the complete 3D design ecosystem.  In doing so, its co-design platform enables a revolutionary approach to integrating with physical implementation tools in both IC and Package design spaces, as well as performing signal, power integrity and thermal analysis for physical-aware and simulation-aware system interconnect optimization.

She also demonstrated GENIO’s novel approach to creating never-before-seen levels of IC system integration that shortens the design cycle by two orders of magnitude, drives faster time-to-manufacturing, improves yields, and streamlines the entire IC eco-system to enable function-intensive IC-designs that will be the backbone for the most advanced next-generation integrated circuits. 

“Shrinking transistors below a 1-nanometer node gets closer to the technology’s limit.  To further scale IC-functionality means moving “off chip” to vertical IC integration. This, Ms. Fontanelli explains, is the most practical way – perhaps the only way – to increase design complexity, reduce time-to-market and lower per unit costs.  Certainly, it’s more economically viable than extreme miniaturization,” she claims. 

During her demonstration, Ms. Fontanelli offered the work that MZ Technologies is doing on Europe Horizon’s NibleAI Research Initiative as proof of GENIO’s capabilities. 

For this project, the 3D EDA tool supports technology-aware 3D physical architecture exploration across layers, a chiplet based floor planning approach enabling the use of multiple IP libraries to quickly explore different combinations of components and system configurations to find the most efficient component stack, and discover interconnection solution with the smallest footprint.  Key is the fact that the tool remains agnostic to the different nature of the components and other tools used implementation and simulation, she explained.

GENIO™ features system architecture exploration, what-if analysis, 3D interconnect management, I/O planning and optimization, integrated within all existing EDA implementation platforms.  It’s optimization algorithms tame the computational complexity of 3D designs. It supports all system architectures (2D, 2.5D, 3D configurations), all assembly styles (wire-bonding, flip-chip, and mixed) and all design flows (die-driven, package-driven, a mixture of top-down & bottom-up).